@InProceedings{MendesCuVaBoCaLiSo:2014:SpMuSB,
               author = "Mendes, C. C. A. and Cunha, G. C. L. and Vasilevski, M. and 
                         Bourguet, V. and Catunda, S. Y. and Lima, R. N. and Souza, 
                         M{\'a}rcia Barros de",
          affiliation = "Department of Electrical Engineering, UFRN, aor3 Natal, RN, 
                         Brazil; National Institute for Space Research, INPE-CRN, Natal, 
                         RN, Brazil and Department of Electrical Engineering, UFRN, aor3 
                         Natal, RN, Brazil; National Institute for Space Research, 
                         INPE-CRN, Natal, RN, Brazil and Department of Electrical 
                         Engineering, UFRN, aor3 Natal, RN, Brazil; National Institute for 
                         Space Research, INPE-CRN, Natal, RN, Brazil and Department of 
                         Electrical Engineering, UFRN, aor3 Natal, RN, Brazil and 
                         Department of Electrical Engineering, UFRN, aor3 Natal, RN, Brazil 
                         and Department of Electrical Engineering, UFBA, Salvador, BA, 
                         Brazil and {Instituto Nacional de Pesquisas Espaciais (INPE)}",
                title = "Specifications for a multi-standard SBCD/ARGOS-3 integrated UHF 
                         satellite receiver",
            booktitle = "Proceedings...",
                 year = "2014",
         organization = "Latin American Symposium on Circuits and Systems (LASCAS), 5.",
            publisher = "IEEE Computer Society",
              address = "Santiago",
             keywords = "CMOS integrated circuits, Low noise amplifiers, Phase locked 
                         loops, Specifications, UHF devices, ARGOS-3, Front-end design, Low 
                         intermediate frequency architecture, Multi-standard, Passive 
                         mixers, Satellite receivers, SBCD, UHF receivers, Ultrahigh 
                         frequency amplifiers.",
             abstract = "The specifications for the front-end design of a SBCD/ARGOS-3 
                         integrated UHF receiver in a 0.13 ¼m star-dard CMOS process are 
                         derived. A low intermediate frequency architecture is presented, 
                         in which a 3-stage low-noise amplifier, a passive mixer and a 
                         phase-locked loop based frequency synthesizer are employed for 
                         achieving the resulting specs. © 2014 IEEE.",
  conference-location = "Santiago",
      conference-year = "feb. 25–28, 2013",
                  doi = "10.1109/LASCAS.2014.6820286",
                  url = "http://dx.doi.org/10.1109/LASCAS.2014.6820286",
                 isbn = "9781479925070",
                label = "scopus 2014-11 MendesCuVaBoCaLiBa:2014:SpMuSB",
             language = "en",
        urlaccessdate = "27 abr. 2024"
}